Embodiments of the present invention relate to a non-volatile memory device, and more specifically, to a technology for increasing the operation reliability of the device.
Memory devices may be classified into a volatile memory device and a non-volatile memory device. The non-volatile memory device includes a non-volatile memory cell capable of preserving stored data even when not powered. For example, the non-volatile memory device may be implemented as a flash random access memory (flash RAM), a phase change random access memory (PCRAM), or the like.
The PCRAM includes a memory cell that is implemented using a phase change material such as germanium antimony tellurium (GST), wherein the GST changes to a crystalline phase or an amorphous phase if heat is applied to the GST, thereby storing data in the memory cell.
A non-volatile memory device (e.g., a magnetic memory, a phase change memory (PCM), or the like) has a data processing speed similar to that of a volatile RAM. The non-volatile memory device also preserves data even when power is turned off.
FIGS. 1A and 1B illustrate a conventional phase change resistor (PCR) element 4.
The PCR element 4 includes a top electrode 1, a bottom electrode 3, and a phase change material (PCM) layer 2 located between the top electrode 1 and the bottom electrode 3. If a voltage and a current are applied to the PCM layer 2, a high temperature is induced in the PCM layer 2, such that an electrical conductive state of the PCM layer 2 changes depending on resistance variation. In this case, the PCM layer 2 may be formed of AgInSbTe. The PCM layer 2 uses chalcogenide, the main components of which are chalcogen elements (e.g., S, Se and Te). In more detail, the PCM layer 2 may be formed of a germanium antimony tellurium alloy (Ge2Sb2Te5) composed of Ge—Sb—Te.
FIGS. 2A and 2B are views showing a phase change principle of the conventional PCR element 4.
Referring to FIG. 2A, if a low current smaller than a threshold value flows in the PCR element 4, the PCM layer 2 has a temperature suitable for a crystalline phase. Therefore, the PCM layer 2 changes to the crystalline phase, such that it is changed to a low-resistance phase material.
On the other hand, as shown in FIG. 2B, if a high current greater than the threshold value flows in the PCR element 4, the PCM layer 2 has a temperature higher than a melting point. Therefore, the PCM layer 2 changes to an amorphous phase, such that it is changed to a high-resistance phase material.
As described above, the PCR element 4 can store data corresponding to two resistance phases as non-volatile data. That is, assuming that one case in which the PCR element 4 is in a low-resistance state corresponds to data “1” and the other case in which the PCR element 4 is in a high-resistance state corresponds to data “0”, the PCR element 4 may store two logic states of data.
FIG. 3 illustrates a write operation of a conventional PCR cell.
Referring to FIG. 3, when a current flows between the top electrode 1 and the bottom electrode 3 of the PCR element 4 for a predetermined time, a high temperature is generated. Therefore, the PCM layer 2 changes from a crystalline phase to an amorphous phase in response to the temperature change to the top electrode 1 and the bottom electrode 3.
In this case, when a low current flows in the PCR element 4 during the predetermined time, the PCM layer 2 has the crystalline phase formed by a low-temperature heating state and the PCR element 4 becomes a low-resistance element having a set state. On the other hand, when a high current flows in the PCR element 4 during the predetermined time, the PCM layer 2 has the amorphous phase formed by a high-temperature heating state and the PCR element 4 becomes a high-resistance element having a reset state. Thus, a difference between two phases is represented by a variation in electrical resistance.
Accordingly, in order to write the set state during the write operation, a low voltage is applied to the PCR element 4 for a long period of time. On the other hand, in order to write the reset state during the write operation, a high voltage is applied to the PCR element 4 for a short period of time.
FIG. 4 is a circuit diagram illustrating a conventional phase change memory device.
Referring to FIG. 4, the conventional phase change memory device includes column switching units C_S(0) and C_S(1) and a plurality of mats. Each mat includes unit cells, each of which is formed at an intersectional area between a bit line BL and a word line WL.
In this case, the column switching unit C_S(0) or C_S(1) is coupled between the bit line BL and a global bit line GBL, and it is controlled by a column selection signal LYSW. The column switching units C_S(0) and C_S(1) are selectively turned on according to the column selection signal LYSW, such that the coupling between the bit line BL and the global bit line GBL is controlled.
During an active mode, only one column selection signal (e.g., LYSW<0:7>) is activated, such that a unit cell C coupled to a corresponding bit line BL is selected.
FIG. 5 illustrates a current path in a cell array of the mat shown in FIG. 4.
Referring to FIG. 5, the conventional cell array includes a unit cell C disposed in an intersectional area between the a bit line BL and a word line WL. The unit cell C includes a phase change resistor (PCR) element GST and a cell switch. In this case, the cell switch may be formed of a diode D, and the diode D may be formed of a PN diode.
One electrode of the PCR element GST is coupled to the bit line BL, and the other electrode thereof is coupled to a P-type region of the diode D. An N-type region of the diode D is coupled to the word line WL.
In the conventional cell array, a low voltage (e.g., a ground voltage VSS) is applied to a selected word line WL2 during a read operation. In addition, a read voltage Vh is applied to a selected bit line BL2, such that a set-state read current Iset or a reset-state read current Ireset flows to the selected word line WL2 through the bit line BL, the PCR element GST and the diode D. A current flow formed during the read operation is denoted by a path A.
A sense-amplifier senses cell data transmitted through the bit line BL2, and compares the sensed cell data with a reference voltage, such that it discriminates whether the sensed cell data corresponds to data “1” or data “0”. When writing data in a cell, a write driver provides a driving voltage corresponding to write data to the bit line BL.
When the bit line BL2 is selected, each non-selected bit lines BL1 and BL3 enters a floating status. Meanwhile, when the word line WL2 is selected, each non-selected word lines WL1 and WL3 maintains a pumping voltage (VPPX) level.
However, assuming that the high pumping voltage (VPPX) is applied to each non-selected word line WL1 or WL3 in the conventional cell array, an OFF leakage current shown by a reference character B may be generated.
That is, while each non-selected word line WL1 or WL3 has the high pumping voltage VPPX level, the selected word line WL2 has a relatively low ground voltage (VSS) level. Therefore, a reverse leakage current flows in a diode of each non-selected cell, such that a voltage level of the selected word line WL2 is unnecessarily increased.
Generally, a resistive memory may include a cell switch. Each unit cell C includes this cell switch. Although the number of cell switches coupled to one bit line BL is changed according to a cell array structure, the number of cell switches is generally set to a very high value “K”.
Assuming that a leakage current occurs in numerous cell switches, a current of about several hundred μA is provided to the bit line BL, such that a voltage level of the bit line BL is increased. Specifically, in case of a structure in which the bit line BL shares two mats, a leakage current generated from two mats flows in the word line WL2, which may induce more serious problems.
In this case, a threshold voltage of a PCR element GST and a cell switch is present between the selected word line WL2 and the non-selected bit line BL1 or BL3.
However, the voltage level of the bit line BL increased by the leakage current is much higher than a voltage level of the word line WL2. Therefore, if the voltage level of the bit line BL is increased, a leakage current (i.e., a leakage path) is generated toward the selected word line WL2. As a result, the voltage level of the selected word line WL2 is increased.
FIG. 6 is a flowchart illustrating the problems encountered in the leakage path.
Referring to FIG. 6, electric charges in the non-selected bit lines BL1 and BL3 are unnecessarily increased by a leakage current generated from diodes of non-selected cells in the conventional cell array at step S1.
That is, electric charges are input to the non-selected bit lines BL1 and BL3 by the switching leakage current of the diodes, and the input electric charges flow toward the selected word line WL2, which induces a faulty operation. Specifically, an unexpected current may flow through a non-selected bit line during an operation of the memory device having a relatively long sensing time, and the unexpected current may cause the faulty operation.
Thus, the voltage level of the selected word line WL2 is increased by the input electric charges at step S2. Accordingly, the capability of a row selection switch LXSW (not shown) for selecting a corresponding word line among a plurality of word lines may be deteriorated at step S3.
As a result, a path of current flowing to the selected word line WL2 is disturbed at step S4. That is, a faulty operation may be caused by the leakage current generated in the operation of the memory device, and thus program and read properties and the operation reliability of the memory device may be decreased at step S5.